The present inventive concepts relate to semiconductor circuits, and more particularly, to methods for designing and manufacturing such circuits, and to the physical architecture of the circuits resulting from using such methods.
A significant concern in integrated circuit design is reducing leakage currents. Leakage currents flow in logic circuits from a power supply node into the ground node because the switching characteristics of the transistors in the logic circuits are not ideal (i.e., the transistors cannot be completely shut off). In multi-threshold complementary metal-oxide semiconductor (MTCMOS) circuits, one technique that reduces leakage current is to place a “power gate” (sometimes referred to as a “power switch” or “switch cell”) between a virtual power supply (i.e., “virtual power”) and a primary power reference (i.e., “reference power”) supply.
The power gate is typically a transistor which has a higher threshold voltage than the threshold voltage of the transistors used to implement the logic cells. In one mode, a leakage current flows from a real power supply node through a virtual power supply node, then through a logic cell domain, and then to a true ground node. In another mode, the virtual power supply node of the power gate cuts off the leakage current path from the virtual power node to the true ground node. Logic cells can be arranged in rows. Conventionally, the power switches are placed in alternate rows in a single column to avoid latch up issues. In other words, for a given column of power switches, every other row within the column has associated therewith a power switch. This technique results in an abundance of power switches, congestion, and leakage consumed by the power switches. In this configuration, n-wells in power switch cells need to be biased to the real power supply to be functional, and therefore, the power switch cells are placed in staggered or alternating fashion.
What is needed is an improved power gate switch architecture and technique for reducing power switches and layers while satisfying design requirements.